Qualifier Applications open for January 2027 term, Last date to Apply: January 29, 2027

Qualifier Applications open for January 2027 term, Last date to Apply: January 29, 2027

Diploma Level

Computer Organisation

by Prof. Janakiraman Viraraghavan

Course ID: EE2106

Course Credits: 4

Course Type: Diploma

Pre-requisites: None

Course structure & AssessmentsVIEW COURSE VIDEOS

The course provides an introduction to assembly language programming relating it to C programs via inline assembly. Concepts of compiling, linking, and execution are all dealt with in great detail by using C programs as a vehicle and suitable animations. The course then moves on to introduce the components of a computer system, namely register file, memory, data path and control path. The course then goes on to build a single cycle processor of a load store architecture like RISC-V. The focus of the discussion will revolve around delays and maximum clock frequency of the processor. This leads to multi-cycle processors and eventually pipelined processors. Data and control hazards are discussed in great detail. The course will end with a discussion about virtual memory and introduce various technologies like SRAM/ DRAM and Non-Volatile memory. For details of standard course structure and assessments, visit Academics page.

Week 1 Introduction to x86 architecture and assembly programming; instruction sets, memory organization, and basic data access.
Week 2 Assembly programming fundamentals; jump, stack, call/return, and string instructions.
Week 3 Inline assembly programming; arithmetic operations, string handling, preprocessing, compilation, and linking.
Week 4 Program execution flow; stack organization, parameter passing, calling conventions, and function management.
Week 5 Memory organization and advanced programming concepts; alignment, recursion, pointers, stack behavior, and object-oriented features in C++.
Week 6 Datapath fundamentals; sequential adders, register files, opcodes, timing analysis, and write-back mechanisms.
Week 7 RISC versus CISC architectures; machine code interpretation, instruction formats, and opcode construction.
Week 8 Single-cycle processor design; datapath, control path, instruction execution, and performance analysis.
Week 9 Multicycle and pipelined processor architectures; datapath, control path, and performance trade-offs
Week 10 Pipeline implementation and hazards; data hazards, control hazards, timing analysis, and pipelined processor design.
Week 11 Advanced microarchitecture concepts; instruction extensions, stuck-at fault analysis, and cache memory systems.
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About the Instructors

Prof. Janakiraman Viraraghavan
Assistant Professor, Department of Electrical Engineering, IIT Madras

Prof. Janakiraman Viraraghavan is an Assistant Professor at the Department of Electrical Engineering, IIT Madras and is part of the Integrated Circuits and Systems (iCS) group. His research interests include porting machine-learning algorithms on to hardware and statistical analysis in VLSI. He also has a keen interest in Microprocessors and Programming in general.

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Other courses by the same instructor: EE1101 - Electronic Systems Thinking and Circuits and EE2103 - Digital System Design

View all Diploma Level courses